Thoughts toward synching up the receiver's clock

What has us most pleased about the project (other than the little lightey going on when we push the button) is this original scheme for getting the receiver's clocking frequency and phase matching the sender's. (As it is, we set the receiver's clock frequency by hand by minimizing the LED "duty cycle" when we know the transmitter is sending "0".)

Our (unimplemented) fiendish plan to see whether the clocks are drifting out of phase is this. We clock at what we think are the right rate and phase, but also take readings (e.g. have another decoding shift register clocking) on the falling edges a half-clock ahead and a half-clock behind our data readings. The expected correlations, if we are right on target (i.e. right in the middle of a good data bit) of the "ahead reading" and the "behind reading" should be 75%. We should be centered between the transitions to the next and previous bit. So the half-clock-behind reading should have an equal chance of falling on the current or previous bit, and the same for the half-clock-ahead reading and the current or next bit. On the other hand, the current and previous bits have a 50-50 chance of agreeing already (pseudorandom noise!), so the correlations expected should be 75% (modulo, well, setup-time violations...).

So we can tell if we're on target, on average, by comparing these two correlations. If the correlation of the half-clock-behind reading and the current reading starts to increase, and that of the half-clock-ahead reading and the current reading starts to decrease, this suggests the current clocking rate needs to be decreased. Here is approximately what we're thinking: